Technical Field
The present invention, generally relates to execution of program codes, and more particularly, to execution of program regions with transactional memory support in computer systems.
Related Art
Transactional memory is a programming paradigm for concurrent computing. In such transactional memory programming environment, programmers can simply define program regions that may access shared variables as transactions by using machine instructions, by using compiler-provided programs or by using libraries.
Hardware transactional memory (HTM) is hardware implementation of the transactional memory. The HTM provides high concurrent performance by optimistically executing transactions in parallel. Processers with HTM keep track of memory loads and stores in hardware resources, such as caches, to detect data conflicts and buffer the memory stores during transactions. When the transaction aborts, the execution is rolled back to immediately after the beginning of the transaction or jumps to an abort handler. The transaction abort may occur due to data conflicts, resource conflicts or violations. The aborts that occur when the amount of memory access logs exceeds capacity of the hardware resources is called a capacity overflow abort.
Typical processers with HTM need a software fall back mechanism since the processors do not guarantee that the transactions eventually commit In general, the fall back mechanism uses a single global lock to support any critical sections in programs and to reduce complexity of programming.
For the purpose of reducing the transaction aborts, a self-tuning approach has been demonstrated, which exploits lightweight reinforcement learning techniques to identify optimal configuration in a workload oblivious manner with Intel® Transactional Synchronization Extensions (TSX) (N. Diegues et al. Self-Tuning Intel® Transactional Synchronization Extensions. The Proceedings of the 11 th International Conference on Autonomic Computing (ICAC '14). Jun. 18-20, 2014 Philadelphia. Pa.). By this approach, counters to control the number of retries before reverting to the global lock can be tuned by using the machine learning algorithm.
Some processors support simultaneous-multithreading (SMT), which allows multiple hardware threads to run on a single processor core concurrently. In such SMT environment, the transactions may encounter the capacity-overflow aborts before the amount of logs reaches the capacity of the hardware resource since the SMT threads share the hardware resources for conflict detection and store buffering in each core. If the transaction on the processor core reverts to the global lock due to the resource conflict between the SMT threads, the processer serializes the transactions on all threads including SMT threads on different cores. Such serialization diminishes degree of concurrency in the transactional memory executions. Since the above mentioned related art also employs the global lock, the situation remains unchanged, resulting in serialization of threads over different cores.
Thus, a method, associated computer system and computer program product are needed for executing program regions capable of reducing transaction aborts caused by resource conflicts and avoiding serializations of transactions beyond shared resources.